Active ESD protection circuits for a wide variety of applications are becoming increasingly important, for example in automobile technology. In this case, there is a requirement to also design circuits such as these for considerably higher ESD levels than have hitherto been customary. Active ESD protection circuits are usually triggered by the rise in the ESD signal. In this case, the voltage rise per unit time is detected, and a protection transistor is switched on by means of a drive circuit.
U.S. Pat. No. 6,465,768 discloses an ESD protection means using integrated circuit technology having an n-channel MOS field effect transistor and a parasitic npn bipolar transistor whose collector-emitter path is connected in parallel with the NMOS transistor. In addition, a p-type well having a bias circuit is provided, which bias circuit, in the event of the occurrence of an ESD pulse, triggers a triggering substrate current which, in turn, switches on the parasitic bipolar junction transistor, so that an ESD overvoltage is rapidly discharged at an I/O pin of the circuit. It is often desirable to protect not only a separate I/O pad from the effects of ESD but also the supply line itself.
U.S. Pat. No. 5,559,659 discloses an active protection circuit arrangement comprising an RC element which triggers a downstream inverter chain that drives a protection transistor. In the event of a fault, that is to say when there is an impermissibly high voltage, this overvoltage is discharged to ground by the protection transistor, and downstream subassemblies are thus protected from the high voltage. The transistor can therefore be understood as meaning an actively triggered surge arrester.